kim
209f3a3aef
- USB CDC 경로 복원: #define Serial Serial1 우회 제거 - rp2040js/avr8js/codemirror/xterm/monaco-editor vendor화 - /vendor 정적 라우팅 추가 (Express 5 catch-all 우회) - 부팅 완료 타임아웃 감지 (Serial 출력 없어도 8초 후 RAF 전환) - 리셋 시 Simulator 재생성으로 주변 장치 상태 초기화 - 시리얼 패널의 내부 메시지를 console.log로 이동
1250 lines
46 KiB
JavaScript
1250 lines
46 KiB
JavaScript
import { MAX_HARDWARE_IRQ } from './irq.js';
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import { APB_START_ADDRESS, SIO_START_ADDRESS } from './rp2040.js';
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/* eslint-disable @typescript-eslint/no-unused-vars */
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const EXC_RESET = 1;
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const EXC_NMI = 2;
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const EXC_HARDFAULT = 3;
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const EXC_SVCALL = 11;
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const EXC_PENDSV = 14;
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const EXC_SYSTICK = 15;
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const SYSM_APSR = 0;
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const SYSM_IAPSR = 1;
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const SYSM_EAPSR = 2;
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const SYSM_XPSR = 3;
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const SYSM_IPSR = 5;
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const SYSM_EPSR = 6;
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const SYSM_IEPSR = 7;
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export const SYSM_MSP = 8;
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export const SYSM_PSP = 9;
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export const SYSM_PRIMASK = 16;
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export const SYSM_CONTROL = 20;
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/* eslint-enable @typescript-eslint/no-unused-vars */
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// Lowest possible exception priority
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const LOWEST_PRIORITY = 4;
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var ExecutionMode;
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(function (ExecutionMode) {
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ExecutionMode[ExecutionMode["Mode_Thread"] = 0] = "Mode_Thread";
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ExecutionMode[ExecutionMode["Mode_Handler"] = 1] = "Mode_Handler";
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})(ExecutionMode || (ExecutionMode = {}));
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function signExtend8(value) {
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return (value << 24) >> 24;
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}
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function signExtend16(value) {
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return (value << 16) >> 16;
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}
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const spRegister = 13;
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const pcRegister = 15;
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var StackPointerBank;
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(function (StackPointerBank) {
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StackPointerBank[StackPointerBank["SPmain"] = 0] = "SPmain";
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StackPointerBank[StackPointerBank["SPprocess"] = 1] = "SPprocess";
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})(StackPointerBank || (StackPointerBank = {}));
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const LOG_NAME = 'CortexM0Core';
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export class CortexM0Core {
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constructor(rp2040) {
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this.rp2040 = rp2040;
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this.registers = new Uint32Array(16);
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this.bankedSP = 0;
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this.cycles = 0;
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this.eventRegistered = false;
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this.waiting = false;
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// APSR fields
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this.N = false;
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this.C = false;
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this.Z = false;
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this.V = false;
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// How many bytes to rewind the last break instruction
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this.breakRewind = 0;
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// PRIMASK fields
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this.PM = false;
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// CONTROL fields
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this.SPSEL = StackPointerBank.SPmain;
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this.nPRIV = false;
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this.currentMode = ExecutionMode.Mode_Thread;
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this.IPSR = 0;
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this.interruptNMIMask = 0;
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this.pendingInterrupts = 0;
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this.enabledInterrupts = 0;
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this.interruptPriorities = [0xffffffff, 0x0, 0x0, 0x0];
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this.pendingNMI = false;
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this.pendingPendSV = false;
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this.pendingSVCall = false;
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this.pendingSystick = false;
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this.interruptsUpdated = false;
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this.VTOR = 0;
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this.SHPR2 = 0;
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this.SHPR3 = 0;
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/** Hook to listen for function calls - branch-link (BL/BLX) instructions */
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this.blTaken = (core, blx) => {
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void core; // surpress unused variable warnings
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void blx;
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};
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this.SP = 0xfffffffc;
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this.bankedSP = 0xfffffffc;
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}
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get logger() {
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return this.rp2040.logger;
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}
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reset() {
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this.SP = this.rp2040.readUint32(this.VTOR);
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this.PC = this.rp2040.readUint32(this.VTOR + 4) & 0xfffffffe;
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this.cycles = 0;
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}
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get SP() {
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return this.registers[13];
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}
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set SP(value) {
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this.registers[13] = value & ~0x3;
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}
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get LR() {
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return this.registers[14];
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}
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set LR(value) {
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this.registers[14] = value;
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}
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get PC() {
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return this.registers[15];
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}
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set PC(value) {
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this.registers[15] = value;
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}
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get APSR() {
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return ((this.N ? 0x80000000 : 0) |
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(this.Z ? 0x40000000 : 0) |
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(this.C ? 0x20000000 : 0) |
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(this.V ? 0x10000000 : 0));
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}
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set APSR(value) {
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this.N = !!(value & 0x80000000);
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this.Z = !!(value & 0x40000000);
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this.C = !!(value & 0x20000000);
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this.V = !!(value & 0x10000000);
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}
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get xPSR() {
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return this.APSR | this.IPSR | (1 << 24);
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}
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set xPSR(value) {
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this.APSR = value;
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this.IPSR = value & 0x3f;
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}
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checkCondition(cond) {
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// Evaluate base condition.
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let result = false;
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switch (cond >> 1) {
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case 0b000:
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result = this.Z;
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break;
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case 0b001:
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result = this.C;
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break;
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case 0b010:
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result = this.N;
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break;
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case 0b011:
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result = this.V;
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break;
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case 0b100:
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result = this.C && !this.Z;
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break;
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case 0b101:
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result = this.N === this.V;
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break;
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case 0b110:
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result = this.N === this.V && !this.Z;
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break;
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case 0b111:
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result = true;
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break;
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}
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return cond & 0b1 && cond != 0b1111 ? !result : result;
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}
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readUint32(address) {
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return this.rp2040.readUint32(address);
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}
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readUint16(address) {
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return this.rp2040.readUint16(address);
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}
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readUint8(address) {
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return this.rp2040.readUint8(address);
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}
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writeUint32(address, value) {
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this.rp2040.writeUint32(address, value);
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}
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writeUint16(address, value) {
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this.rp2040.writeUint16(address, value);
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}
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writeUint8(address, value) {
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this.rp2040.writeUint8(address, value);
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}
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switchStack(stack) {
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if (this.SPSEL !== stack) {
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const temp = this.SP;
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this.SP = this.bankedSP;
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this.bankedSP = temp;
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this.SPSEL = stack;
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}
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}
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get SPprocess() {
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return this.SPSEL === StackPointerBank.SPprocess ? this.SP : this.bankedSP;
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}
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set SPprocess(value) {
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if (this.SPSEL === StackPointerBank.SPprocess) {
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this.SP = value;
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}
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else {
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this.bankedSP = value >>> 0;
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}
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}
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get SPmain() {
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return this.SPSEL === StackPointerBank.SPmain ? this.SP : this.bankedSP;
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}
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set SPmain(value) {
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if (this.SPSEL === StackPointerBank.SPmain) {
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this.SP = value;
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}
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else {
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this.bankedSP = value >>> 0;
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}
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}
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exceptionEntry(exceptionNumber) {
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// PushStack:
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let framePtr = 0;
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let framePtrAlign = 0;
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if (this.SPSEL && this.currentMode === ExecutionMode.Mode_Thread) {
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framePtrAlign = this.SPprocess & 0b100 ? 1 : 0;
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this.SPprocess = (this.SPprocess - 0x20) & ~0b100;
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framePtr = this.SPprocess;
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}
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else {
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framePtrAlign = this.SPmain & 0b100 ? 1 : 0;
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this.SPmain = (this.SPmain - 0x20) & ~0b100;
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framePtr = this.SPmain;
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}
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/* only the stack locations, not the store order, are architected */
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this.writeUint32(framePtr, this.registers[0]);
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this.writeUint32(framePtr + 0x4, this.registers[1]);
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this.writeUint32(framePtr + 0x8, this.registers[2]);
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this.writeUint32(framePtr + 0xc, this.registers[3]);
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this.writeUint32(framePtr + 0x10, this.registers[12]);
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this.writeUint32(framePtr + 0x14, this.LR);
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this.writeUint32(framePtr + 0x18, this.PC & ~1); // ReturnAddress(ExceptionType);
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this.writeUint32(framePtr + 0x1c, (this.xPSR & ~(1 << 9)) | (framePtrAlign << 9));
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if (this.currentMode == ExecutionMode.Mode_Handler) {
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this.LR = 0xfffffff1;
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}
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else {
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if (!this.SPSEL) {
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this.LR = 0xfffffff9;
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}
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else {
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this.LR = 0xfffffffd;
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}
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}
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// ExceptionTaken:
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this.currentMode = ExecutionMode.Mode_Handler; // Enter Handler Mode, now Privileged
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this.IPSR = exceptionNumber;
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this.switchStack(StackPointerBank.SPmain);
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this.eventRegistered = true;
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const vectorTable = this.VTOR;
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this.PC = this.readUint32(vectorTable + 4 * exceptionNumber);
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}
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exceptionReturn(excReturn) {
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let framePtr = this.SPmain;
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switch (excReturn & 0xf) {
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case 0b0001: // Return to Handler
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this.currentMode = ExecutionMode.Mode_Handler;
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this.switchStack(StackPointerBank.SPmain);
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break;
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case 0b1001: // Return to Thread using Main stack
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this.currentMode = ExecutionMode.Mode_Thread;
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this.switchStack(StackPointerBank.SPmain);
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break;
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case 0b1101: // Return to Thread using Process stack
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framePtr = this.SPprocess;
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this.currentMode = ExecutionMode.Mode_Thread;
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this.switchStack(StackPointerBank.SPprocess);
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break;
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// Assigning CurrentMode to Mode_Thread causes a drop in privilege
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// if CONTROL.nPRIV is set to 1
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}
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// PopStack:
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this.registers[0] = this.readUint32(framePtr); // Stack accesses are performed as Unprivileged accesses if
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this.registers[1] = this.readUint32(framePtr + 0x4); // CONTROL<0>=='1' && EXC_RETURN<3>=='1' Privileged otherwise
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this.registers[2] = this.readUint32(framePtr + 0x8);
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this.registers[3] = this.readUint32(framePtr + 0xc);
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this.registers[12] = this.readUint32(framePtr + 0x10);
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this.LR = this.readUint32(framePtr + 0x14);
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this.PC = this.readUint32(framePtr + 0x18);
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const psr = this.readUint32(framePtr + 0x1c);
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const framePtrAlign = psr & (1 << 9) ? 0b100 : 0;
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switch (excReturn & 0xf) {
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case 0b0001: // Returning to Handler mode
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this.SPmain = (this.SPmain + 0x20) | framePtrAlign;
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break;
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case 0b1001: // Returning to Thread mode using Main stack
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this.SPmain = (this.SPmain + 0x20) | framePtrAlign;
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break;
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case 0b1101: // Returning to Thread mode using Process stack
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this.SPprocess = (this.SPprocess + 0x20) | framePtrAlign;
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break;
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}
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this.APSR = psr & 0xf0000000;
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const forceThread = this.currentMode == ExecutionMode.Mode_Thread && this.nPRIV;
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this.IPSR = forceThread ? 0 : psr & 0x3f;
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this.interruptsUpdated = true;
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// Thumb bit should always be one! EPSR<24> = psr<24>; // Load valid EPSR bits from memory
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this.eventRegistered = true;
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// if CurrentMode == Mode_Thread && SCR.SLEEPONEXIT == '1' then
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// SleepOnExit(); // IMPLEMENTATION DEFINED
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}
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get pendSVPriority() {
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return (this.SHPR3 >> 22) & 0x3;
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}
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get svCallPriority() {
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return this.SHPR2 >>> 30;
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}
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get systickPriority() {
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return this.SHPR3 >>> 30;
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}
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exceptionPriority(n) {
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switch (n) {
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case EXC_RESET:
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return -3;
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case EXC_NMI:
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return -2;
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case EXC_HARDFAULT:
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return -1;
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case EXC_SVCALL:
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return this.svCallPriority;
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case EXC_PENDSV:
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return this.pendSVPriority;
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case EXC_SYSTICK:
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return this.systickPriority;
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default: {
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if (n < 16) {
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return LOWEST_PRIORITY;
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}
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const intNum = n - 16;
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for (let priority = 0; priority < 4; priority++) {
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if (this.interruptPriorities[priority] & (1 << intNum)) {
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return priority;
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}
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}
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return LOWEST_PRIORITY;
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}
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}
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}
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get vectPending() {
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if (this.pendingNMI) {
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return EXC_NMI;
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}
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const { svCallPriority, systickPriority, pendSVPriority, pendingInterrupts } = this;
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for (let priority = 0; priority < LOWEST_PRIORITY; priority++) {
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const levelInterrupts = pendingInterrupts & this.interruptPriorities[priority];
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if (this.pendingSVCall && priority === svCallPriority) {
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return EXC_SVCALL;
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}
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if (this.pendingPendSV && priority === pendSVPriority) {
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return EXC_PENDSV;
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}
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if (this.pendingSystick && priority === systickPriority) {
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return EXC_SYSTICK;
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}
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if (levelInterrupts) {
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for (let interruptNumber = 0; interruptNumber < 32; interruptNumber++) {
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if (levelInterrupts & (1 << interruptNumber)) {
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return 16 + interruptNumber;
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}
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}
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}
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}
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return 0;
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}
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setInterrupt(irq, value) {
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const irqBit = 1 << irq;
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if (value && !(this.pendingInterrupts & irqBit)) {
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this.pendingInterrupts |= irqBit;
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this.interruptsUpdated = true;
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if (this.waiting && this.checkForInterrupts()) {
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this.waiting = false;
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}
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}
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else if (!value) {
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this.pendingInterrupts &= ~irqBit;
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}
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}
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checkForInterrupts() {
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/* If we're waiting for an interrupt (i.e. WFI/WFE), the ARM says:
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> If PRIMASK.PM is set to 1, an asynchronous exception that has a higher group priority than any
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> active exception results in a WFI instruction exit. If the group priority of the exception is less than or
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> equal to the execution group priority, the exception is ignored.
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*/
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const currentPriority = this.waiting
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? this.PM
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? this.exceptionPriority(this.IPSR)
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: LOWEST_PRIORITY
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: Math.min(this.exceptionPriority(this.IPSR), this.PM ? 0 : LOWEST_PRIORITY);
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const interruptSet = this.pendingInterrupts & this.enabledInterrupts;
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const { svCallPriority, systickPriority, pendSVPriority } = this;
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if (this.pendingNMI) {
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this.pendingNMI = false;
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this.exceptionEntry(EXC_NMI);
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return true;
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}
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for (let priority = 0; priority < currentPriority; priority++) {
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const levelInterrupts = interruptSet & this.interruptPriorities[priority];
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if (this.pendingSVCall && priority === svCallPriority) {
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this.pendingSVCall = false;
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this.exceptionEntry(EXC_SVCALL);
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return true;
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}
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if (this.pendingPendSV && priority === pendSVPriority) {
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this.pendingPendSV = false;
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this.exceptionEntry(EXC_PENDSV);
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return true;
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}
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if (this.pendingSystick && priority === systickPriority) {
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this.pendingSystick = false;
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this.exceptionEntry(EXC_SYSTICK);
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return true;
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}
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if (levelInterrupts) {
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for (let interruptNumber = 0; interruptNumber < 32; interruptNumber++) {
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if (levelInterrupts & (1 << interruptNumber)) {
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if (interruptNumber > MAX_HARDWARE_IRQ) {
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this.pendingInterrupts &= ~(1 << interruptNumber);
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}
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this.exceptionEntry(16 + interruptNumber);
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return true;
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}
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}
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}
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}
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this.interruptsUpdated = false;
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return false;
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}
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readSpecialRegister(sysm) {
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switch (sysm) {
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case SYSM_APSR:
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return this.APSR;
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case SYSM_XPSR:
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return this.xPSR;
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case SYSM_IPSR:
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return this.IPSR;
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case SYSM_PRIMASK:
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return this.PM ? 1 : 0;
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case SYSM_MSP:
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return this.SPmain;
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case SYSM_PSP:
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return this.SPprocess;
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case SYSM_CONTROL:
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return (this.SPSEL === StackPointerBank.SPprocess ? 2 : 0) | (this.nPRIV ? 1 : 0);
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default:
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this.logger.warn(LOG_NAME, `MRS with unimplemented SYSm value: ${sysm}`);
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return 0;
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}
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}
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writeSpecialRegister(sysm, value) {
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switch (sysm) {
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case SYSM_APSR:
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this.APSR = value;
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break;
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case SYSM_XPSR:
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this.xPSR = value;
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break;
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case SYSM_IPSR:
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this.IPSR = value;
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break;
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case SYSM_PRIMASK:
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this.PM = !!(value & 1);
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this.interruptsUpdated = true;
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break;
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case SYSM_MSP:
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this.SPmain = value;
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break;
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case SYSM_PSP:
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this.SPprocess = value;
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break;
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case SYSM_CONTROL:
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this.nPRIV = !!(value & 1);
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if (this.currentMode === ExecutionMode.Mode_Thread) {
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this.switchStack(value & 2 ? StackPointerBank.SPprocess : StackPointerBank.SPmain);
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}
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break;
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default:
|
|
this.logger.warn(LOG_NAME, `MRS with unimplemented SYSm value: ${sysm}`);
|
|
return 0;
|
|
}
|
|
}
|
|
BXWritePC(address) {
|
|
if (this.currentMode == ExecutionMode.Mode_Handler && address >>> 28 == 0b1111) {
|
|
this.exceptionReturn(address & 0x0fffffff);
|
|
}
|
|
else {
|
|
this.PC = address & ~1;
|
|
}
|
|
}
|
|
substractUpdateFlags(minuend, subtrahend) {
|
|
const result = minuend - subtrahend;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
this.C = minuend >= subtrahend;
|
|
this.V =
|
|
(!!(result & 0x80000000) && !(minuend & 0x80000000) && !!(subtrahend & 0x80000000)) ||
|
|
(!(result & 0x80000000) && !!(minuend & 0x80000000) && !(subtrahend & 0x80000000));
|
|
return result;
|
|
}
|
|
addUpdateFlags(addend1, addend2) {
|
|
const unsignedSum = (addend1 + addend2) >>> 0;
|
|
const signedSum = (addend1 | 0) + (addend2 | 0);
|
|
const result = addend1 + addend2;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
this.C = result === unsignedSum ? false : true;
|
|
this.V = (result | 0) === signedSum ? false : true;
|
|
return result & 0xffffffff;
|
|
}
|
|
cyclesIO(addr, write = false) {
|
|
addr = addr >>> 0;
|
|
if (addr >= SIO_START_ADDRESS && addr < SIO_START_ADDRESS + 0x10000000) {
|
|
return 0;
|
|
}
|
|
if (addr >= APB_START_ADDRESS && addr < APB_START_ADDRESS + 0x10000000) {
|
|
return write ? 4 : 3;
|
|
}
|
|
return 1;
|
|
}
|
|
executeInstruction() {
|
|
if (this.interruptsUpdated) {
|
|
if (this.checkForInterrupts()) {
|
|
this.waiting = false;
|
|
}
|
|
}
|
|
// ARM Thumb instruction encoding - 16 bits / 2 bytes
|
|
const opcodePC = this.PC & ~1; //ensure no LSB set PC are executed
|
|
const opcode = this.readUint16(opcodePC);
|
|
const wideInstruction = opcode >> 12 === 0b1111 || opcode >> 11 === 0b11101;
|
|
const opcode2 = wideInstruction ? this.readUint16(opcodePC + 2) : 0;
|
|
this.PC += 2;
|
|
let deltaCycles = 1;
|
|
// ADCS
|
|
if (opcode >> 6 === 0b0100000101) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
this.registers[Rdn] = this.addUpdateFlags(this.registers[Rm], this.registers[Rdn] + (this.C ? 1 : 0));
|
|
}
|
|
// ADD (register = SP plus immediate)
|
|
else if (opcode >> 11 === 0b10101) {
|
|
const imm8 = opcode & 0xff;
|
|
const Rd = (opcode >> 8) & 0x7;
|
|
this.registers[Rd] = this.SP + (imm8 << 2);
|
|
}
|
|
// ADD (SP plus immediate)
|
|
else if (opcode >> 7 === 0b101100000) {
|
|
const imm32 = (opcode & 0x7f) << 2;
|
|
this.SP += imm32;
|
|
}
|
|
// ADDS (Encoding T1)
|
|
else if (opcode >> 9 === 0b0001110) {
|
|
const imm3 = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.addUpdateFlags(this.registers[Rn], imm3);
|
|
}
|
|
// ADDS (Encoding T2)
|
|
else if (opcode >> 11 === 0b00110) {
|
|
const imm8 = opcode & 0xff;
|
|
const Rdn = (opcode >> 8) & 0x7;
|
|
this.registers[Rdn] = this.addUpdateFlags(this.registers[Rdn], imm8);
|
|
}
|
|
// ADDS (register)
|
|
else if (opcode >> 9 === 0b0001100) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.addUpdateFlags(this.registers[Rn], this.registers[Rm]);
|
|
}
|
|
// ADD (register)
|
|
else if (opcode >> 8 === 0b01000100) {
|
|
const Rm = (opcode >> 3) & 0xf;
|
|
const Rdn = ((opcode & 0x80) >> 4) | (opcode & 0x7);
|
|
const leftValue = Rdn === pcRegister ? this.PC + 2 : this.registers[Rdn];
|
|
const rightValue = Rm === pcRegister ? this.PC + 2 : this.registers[Rm];
|
|
const result = leftValue + rightValue;
|
|
if (Rdn !== spRegister && Rdn !== pcRegister) {
|
|
this.registers[Rdn] = result;
|
|
}
|
|
else if (Rdn === pcRegister) {
|
|
this.registers[Rdn] = result & ~0x1;
|
|
deltaCycles++;
|
|
}
|
|
else if (Rdn === spRegister) {
|
|
this.registers[Rdn] = result & ~0x3;
|
|
}
|
|
}
|
|
// ADR
|
|
else if (opcode >> 11 === 0b10100) {
|
|
const imm8 = opcode & 0xff;
|
|
const Rd = (opcode >> 8) & 0x7;
|
|
this.registers[Rd] = (opcodePC & 0xfffffffc) + 4 + (imm8 << 2);
|
|
}
|
|
// ANDS (Encoding T2)
|
|
else if (opcode >> 6 === 0b0100000000) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const result = this.registers[Rdn] & this.registers[Rm];
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
}
|
|
// ASRS (immediate)
|
|
else if (opcode >> 11 === 0b00010) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
const shiftN = imm5 ? imm5 : 32;
|
|
const result = shiftN < 32 ? input >> shiftN : (input & 0x80000000) >> 31;
|
|
this.registers[Rd] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
this.C = input & (1 << (shiftN - 1)) ? true : false;
|
|
}
|
|
// ASRS (register)
|
|
else if (opcode >> 6 === 0b0100000100) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const input = this.registers[Rdn];
|
|
const shiftN = (this.registers[Rm] & 0xff) < 32 ? this.registers[Rm] & 0xff : 32;
|
|
const result = shiftN < 32 ? input >> shiftN : (input & 0x80000000) >> 31;
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
this.C = input & (1 << (shiftN - 1)) ? true : false;
|
|
}
|
|
// B (with cond)
|
|
else if (opcode >> 12 === 0b1101 && ((opcode >> 9) & 0x7) !== 0b111) {
|
|
let imm8 = (opcode & 0xff) << 1;
|
|
const cond = (opcode >> 8) & 0xf;
|
|
if (imm8 & (1 << 8)) {
|
|
imm8 = (imm8 & 0x1ff) - 0x200;
|
|
}
|
|
if (this.checkCondition(cond)) {
|
|
this.PC += imm8 + 2;
|
|
deltaCycles++;
|
|
}
|
|
}
|
|
// B
|
|
else if (opcode >> 11 === 0b11100) {
|
|
let imm11 = (opcode & 0x7ff) << 1;
|
|
if (imm11 & (1 << 11)) {
|
|
imm11 = (imm11 & 0x7ff) - 0x800;
|
|
}
|
|
this.PC += imm11 + 2;
|
|
deltaCycles++;
|
|
}
|
|
// BICS
|
|
else if (opcode >> 6 === 0b0100001110) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const result = (this.registers[Rdn] &= ~this.registers[Rm]);
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
}
|
|
// BKPT
|
|
else if (opcode >> 8 === 0b10111110) {
|
|
const imm8 = opcode & 0xff;
|
|
this.breakRewind = 2;
|
|
this.rp2040.onBreak(imm8);
|
|
}
|
|
// BL
|
|
else if (opcode >> 11 === 0b11110 && opcode2 >> 14 === 0b11 && ((opcode2 >> 12) & 0x1) == 1) {
|
|
const imm11 = opcode2 & 0x7ff;
|
|
const J2 = (opcode2 >> 11) & 0x1;
|
|
const J1 = (opcode2 >> 13) & 0x1;
|
|
const imm10 = opcode & 0x3ff;
|
|
const S = (opcode >> 10) & 0x1;
|
|
const I1 = 1 - (S ^ J1);
|
|
const I2 = 1 - (S ^ J2);
|
|
const imm32 = ((S ? 0b11111111 : 0) << 24) | ((I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1));
|
|
this.LR = (this.PC + 2) | 0x1;
|
|
this.PC += 2 + imm32;
|
|
deltaCycles += 2;
|
|
this.blTaken(this, false);
|
|
}
|
|
// BLX
|
|
else if (opcode >> 7 === 0b010001111 && (opcode & 0x7) === 0) {
|
|
const Rm = (opcode >> 3) & 0xf;
|
|
this.LR = this.PC | 0x1;
|
|
this.PC = this.registers[Rm] & ~1;
|
|
deltaCycles++;
|
|
this.blTaken(this, true);
|
|
}
|
|
// BX
|
|
else if (opcode >> 7 === 0b010001110 && (opcode & 0x7) === 0) {
|
|
const Rm = (opcode >> 3) & 0xf;
|
|
this.BXWritePC(this.registers[Rm]);
|
|
deltaCycles++;
|
|
}
|
|
// CMN (register)
|
|
else if (opcode >> 6 === 0b0100001011) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rn = opcode & 0x7;
|
|
this.addUpdateFlags(this.registers[Rn], this.registers[Rm]);
|
|
}
|
|
// CMP immediate
|
|
else if (opcode >> 11 === 0b00101) {
|
|
const Rn = (opcode >> 8) & 0x7;
|
|
const imm8 = opcode & 0xff;
|
|
this.substractUpdateFlags(this.registers[Rn], imm8);
|
|
}
|
|
// CMP (register)
|
|
else if (opcode >> 6 === 0b0100001010) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rn = opcode & 0x7;
|
|
this.substractUpdateFlags(this.registers[Rn], this.registers[Rm]);
|
|
}
|
|
// CMP (register) encoding T2
|
|
else if (opcode >> 8 === 0b01000101) {
|
|
const Rm = (opcode >> 3) & 0xf;
|
|
const Rn = ((opcode >> 4) & 0x8) | (opcode & 0x7);
|
|
this.substractUpdateFlags(this.registers[Rn], this.registers[Rm]);
|
|
}
|
|
// CPSID i
|
|
else if (opcode === 0xb672) {
|
|
this.PM = true;
|
|
}
|
|
// CPSIE i
|
|
else if (opcode === 0xb662) {
|
|
this.PM = false;
|
|
this.interruptsUpdated = true;
|
|
}
|
|
// DMB SY
|
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f50) {
|
|
this.PC += 2;
|
|
deltaCycles += 2;
|
|
}
|
|
// DSB SY
|
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f40) {
|
|
this.PC += 2;
|
|
deltaCycles += 2;
|
|
}
|
|
// EORS
|
|
else if (opcode >> 6 === 0b0100000001) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const result = this.registers[Rm] ^ this.registers[Rdn];
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
}
|
|
// ISB SY
|
|
else if (opcode === 0xf3bf && (opcode2 & 0xfff0) === 0x8f60) {
|
|
this.PC += 2;
|
|
deltaCycles += 2;
|
|
}
|
|
// LDMIA
|
|
else if (opcode >> 11 === 0b11001) {
|
|
const Rn = (opcode >> 8) & 0x7;
|
|
const registers = opcode & 0xff;
|
|
let address = this.registers[Rn];
|
|
for (let i = 0; i < 8; i++) {
|
|
if (registers & (1 << i)) {
|
|
this.registers[i] = this.readUint32(address);
|
|
address += 4;
|
|
deltaCycles++;
|
|
}
|
|
}
|
|
// Write back
|
|
if (!(registers & (1 << Rn))) {
|
|
this.registers[Rn] = address;
|
|
}
|
|
}
|
|
// LDR (immediate)
|
|
else if (opcode >> 11 === 0b01101) {
|
|
const imm5 = ((opcode >> 6) & 0x1f) << 2;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rn] + imm5;
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint32(addr);
|
|
}
|
|
// LDR (sp + immediate)
|
|
else if (opcode >> 11 === 0b10011) {
|
|
const Rt = (opcode >> 8) & 0x7;
|
|
const imm8 = opcode & 0xff;
|
|
const addr = this.SP + (imm8 << 2);
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint32(addr);
|
|
}
|
|
// LDR (literal)
|
|
else if (opcode >> 11 === 0b01001) {
|
|
const imm8 = (opcode & 0xff) << 2;
|
|
const Rt = (opcode >> 8) & 7;
|
|
const nextPC = this.PC + 2;
|
|
const addr = (nextPC & 0xfffffffc) + imm8;
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint32(addr);
|
|
}
|
|
// LDR (register)
|
|
else if (opcode >> 9 === 0b0101100) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint32(addr);
|
|
}
|
|
// LDRB (immediate)
|
|
else if (opcode >> 11 === 0b01111) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rn] + imm5;
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint8(addr);
|
|
}
|
|
// LDRB (register)
|
|
else if (opcode >> 9 === 0b0101110) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint8(addr);
|
|
}
|
|
// LDRH (immediate)
|
|
else if (opcode >> 11 === 0b10001) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rn] + (imm5 << 1);
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint16(addr);
|
|
}
|
|
// LDRH (register)
|
|
else if (opcode >> 9 === 0b0101101) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = this.readUint16(addr);
|
|
}
|
|
// LDRSB
|
|
else if (opcode >> 9 === 0b0101011) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = signExtend8(this.readUint8(addr));
|
|
}
|
|
// LDRSH
|
|
else if (opcode >> 9 === 0b0101111) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const addr = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(addr);
|
|
this.registers[Rt] = signExtend16(this.readUint16(addr));
|
|
}
|
|
// LSLS (immediate)
|
|
else if (opcode >> 11 === 0b00000) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
const result = input << imm5;
|
|
this.registers[Rd] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
this.C = imm5 ? !!(input & (1 << (32 - imm5))) : this.C;
|
|
}
|
|
// LSLS (register)
|
|
else if (opcode >> 6 === 0b0100000010) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const input = this.registers[Rdn];
|
|
const shiftCount = this.registers[Rm] & 0xff;
|
|
const result = shiftCount >= 32 ? 0 : input << shiftCount;
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
this.C = shiftCount ? !!(input & (1 << (32 - shiftCount))) : this.C;
|
|
}
|
|
// LSRS (immediate)
|
|
else if (opcode >> 11 === 0b00001) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
const result = imm5 ? input >>> imm5 : 0;
|
|
this.registers[Rd] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
this.C = !!((input >>> (imm5 ? imm5 - 1 : 31)) & 0x1);
|
|
}
|
|
// LSRS (register)
|
|
else if (opcode >> 6 === 0b0100000011) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const shiftAmount = this.registers[Rm] & 0xff;
|
|
const input = this.registers[Rdn];
|
|
const result = shiftAmount < 32 ? input >>> shiftAmount : 0;
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
this.C = shiftAmount <= 32 ? !!((input >>> (shiftAmount - 1)) & 0x1) : false;
|
|
}
|
|
// MOV
|
|
else if (opcode >> 8 === 0b01000110) {
|
|
const Rm = (opcode >> 3) & 0xf;
|
|
const Rd = ((opcode >> 4) & 0x8) | (opcode & 0x7);
|
|
let value = Rm === pcRegister ? this.PC + 2 : this.registers[Rm];
|
|
if (Rd === pcRegister) {
|
|
deltaCycles++;
|
|
value &= ~1;
|
|
}
|
|
else if (Rd === spRegister) {
|
|
value &= ~3;
|
|
}
|
|
this.registers[Rd] = value;
|
|
}
|
|
// MOVS
|
|
else if (opcode >> 11 === 0b00100) {
|
|
const value = opcode & 0xff;
|
|
const Rd = (opcode >> 8) & 7;
|
|
this.registers[Rd] = value;
|
|
this.N = !!(value & 0x80000000);
|
|
this.Z = value === 0;
|
|
}
|
|
// MRS
|
|
else if (opcode === 0b1111001111101111 && opcode2 >> 12 == 0b1000) {
|
|
const SYSm = opcode2 & 0xff;
|
|
const Rd = (opcode2 >> 8) & 0xf;
|
|
this.registers[Rd] = this.readSpecialRegister(SYSm);
|
|
this.PC += 2;
|
|
deltaCycles += 2;
|
|
}
|
|
// MSR
|
|
else if (opcode >> 4 === 0b111100111000 && opcode2 >> 8 == 0b10001000) {
|
|
const SYSm = opcode2 & 0xff;
|
|
const Rn = opcode & 0xf;
|
|
this.writeSpecialRegister(SYSm, this.registers[Rn]);
|
|
this.PC += 2;
|
|
deltaCycles += 2;
|
|
}
|
|
// MULS
|
|
else if (opcode >> 6 === 0b0100001101) {
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rdm = opcode & 0x7;
|
|
const result = Math.imul(this.registers[Rn], this.registers[Rdm]);
|
|
this.registers[Rdm] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
}
|
|
// MVNS
|
|
else if (opcode >> 6 === 0b0100001111) {
|
|
const Rm = (opcode >> 3) & 7;
|
|
const Rd = opcode & 7;
|
|
const result = ~this.registers[Rm];
|
|
this.registers[Rd] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
}
|
|
// ORRS (Encoding T2)
|
|
else if (opcode >> 6 === 0b0100001100) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const result = this.registers[Rdn] | this.registers[Rm];
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = (result & 0xffffffff) === 0;
|
|
}
|
|
// POP
|
|
else if (opcode >> 9 === 0b1011110) {
|
|
const P = (opcode >> 8) & 1;
|
|
let address = this.SP;
|
|
for (let i = 0; i <= 7; i++) {
|
|
if (opcode & (1 << i)) {
|
|
this.registers[i] = this.readUint32(address);
|
|
address += 4;
|
|
deltaCycles++;
|
|
}
|
|
}
|
|
if (P) {
|
|
this.SP = address + 4;
|
|
this.BXWritePC(this.readUint32(address));
|
|
deltaCycles += 2;
|
|
}
|
|
else {
|
|
this.SP = address;
|
|
}
|
|
}
|
|
// PUSH
|
|
else if (opcode >> 9 === 0b1011010) {
|
|
let bitCount = 0;
|
|
for (let i = 0; i <= 8; i++) {
|
|
if (opcode & (1 << i)) {
|
|
bitCount++;
|
|
}
|
|
}
|
|
let address = this.SP - 4 * bitCount;
|
|
for (let i = 0; i <= 7; i++) {
|
|
if (opcode & (1 << i)) {
|
|
this.writeUint32(address, this.registers[i]);
|
|
deltaCycles++;
|
|
address += 4;
|
|
}
|
|
}
|
|
if (opcode & (1 << 8)) {
|
|
this.writeUint32(address, this.registers[14]);
|
|
}
|
|
this.SP -= 4 * bitCount;
|
|
}
|
|
// REV
|
|
else if (opcode >> 6 === 0b1011101000) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
this.registers[Rd] =
|
|
((input & 0xff) << 24) |
|
|
(((input >> 8) & 0xff) << 16) |
|
|
(((input >> 16) & 0xff) << 8) |
|
|
((input >> 24) & 0xff);
|
|
}
|
|
// REV16
|
|
else if (opcode >> 6 === 0b1011101001) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
this.registers[Rd] =
|
|
(((input >> 16) & 0xff) << 24) |
|
|
(((input >> 24) & 0xff) << 16) |
|
|
((input & 0xff) << 8) |
|
|
((input >> 8) & 0xff);
|
|
}
|
|
// REVSH
|
|
else if (opcode >> 6 === 0b1011101011) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
const input = this.registers[Rm];
|
|
this.registers[Rd] = signExtend16(((input & 0xff) << 8) | ((input >> 8) & 0xff));
|
|
}
|
|
// ROR
|
|
else if (opcode >> 6 === 0b0100000111) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
const input = this.registers[Rdn];
|
|
const shift = (this.registers[Rm] & 0xff) % 32;
|
|
const result = (input >>> shift) | (input << (32 - shift));
|
|
this.registers[Rdn] = result;
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
this.C = !!(result & 0x80000000);
|
|
}
|
|
// NEGS / RSBS
|
|
else if (opcode >> 6 === 0b0100001001) {
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.substractUpdateFlags(0, this.registers[Rn]);
|
|
}
|
|
// NOP
|
|
else if (opcode === 0b1011111100000000) {
|
|
// Do nothing!
|
|
}
|
|
// SBCS (Encoding T1)
|
|
else if (opcode >> 6 === 0b0100000110) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rdn = opcode & 0x7;
|
|
this.registers[Rdn] = this.substractUpdateFlags(this.registers[Rdn], this.registers[Rm] + (1 - (this.C ? 1 : 0)));
|
|
}
|
|
// SEV
|
|
else if (opcode === 0b1011111101000000) {
|
|
this.logger.info(LOG_NAME, 'SEV');
|
|
}
|
|
// STMIA
|
|
else if (opcode >> 11 === 0b11000) {
|
|
const Rn = (opcode >> 8) & 0x7;
|
|
const registers = opcode & 0xff;
|
|
let address = this.registers[Rn];
|
|
for (let i = 0; i < 8; i++) {
|
|
if (registers & (1 << i)) {
|
|
this.writeUint32(address, this.registers[i]);
|
|
address += 4;
|
|
deltaCycles++;
|
|
}
|
|
}
|
|
// Write back
|
|
if (!(registers & (1 << Rn))) {
|
|
this.registers[Rn] = address;
|
|
}
|
|
}
|
|
// STR (immediate)
|
|
else if (opcode >> 11 === 0b01100) {
|
|
const imm5 = ((opcode >> 6) & 0x1f) << 2;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rn] + imm5;
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint32(address, this.registers[Rt]);
|
|
}
|
|
// STR (sp + immediate)
|
|
else if (opcode >> 11 === 0b10010) {
|
|
const Rt = (opcode >> 8) & 0x7;
|
|
const imm8 = opcode & 0xff;
|
|
const address = this.SP + (imm8 << 2);
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint32(address, this.registers[Rt]);
|
|
}
|
|
// STR (register)
|
|
else if (opcode >> 9 === 0b0101000) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint32(address, this.registers[Rt]);
|
|
}
|
|
// STRB (immediate)
|
|
else if (opcode >> 11 === 0b01110) {
|
|
const imm5 = (opcode >> 6) & 0x1f;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rn] + imm5;
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint8(address, this.registers[Rt]);
|
|
}
|
|
// STRB (register)
|
|
else if (opcode >> 9 === 0b0101010) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint8(address, this.registers[Rt]);
|
|
}
|
|
// STRH (immediate)
|
|
else if (opcode >> 11 === 0b10000) {
|
|
const imm5 = ((opcode >> 6) & 0x1f) << 1;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rn] + imm5;
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint16(address, this.registers[Rt]);
|
|
}
|
|
// STRH (register)
|
|
else if (opcode >> 9 === 0b0101001) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rt = opcode & 0x7;
|
|
const address = this.registers[Rm] + this.registers[Rn];
|
|
deltaCycles += this.cyclesIO(address, true);
|
|
this.writeUint16(address, this.registers[Rt]);
|
|
}
|
|
// SUB (SP minus immediate)
|
|
else if (opcode >> 7 === 0b101100001) {
|
|
const imm32 = (opcode & 0x7f) << 2;
|
|
this.SP -= imm32;
|
|
}
|
|
// SUBS (Encoding T1)
|
|
else if (opcode >> 9 === 0b0001111) {
|
|
const imm3 = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.substractUpdateFlags(this.registers[Rn], imm3);
|
|
}
|
|
// SUBS (Encoding T2)
|
|
else if (opcode >> 11 === 0b00111) {
|
|
const imm8 = opcode & 0xff;
|
|
const Rdn = (opcode >> 8) & 0x7;
|
|
this.registers[Rdn] = this.substractUpdateFlags(this.registers[Rdn], imm8);
|
|
}
|
|
// SUBS (register)
|
|
else if (opcode >> 9 === 0b0001101) {
|
|
const Rm = (opcode >> 6) & 0x7;
|
|
const Rn = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.substractUpdateFlags(this.registers[Rn], this.registers[Rm]);
|
|
}
|
|
// SVC
|
|
else if (opcode >> 8 === 0b11011111) {
|
|
this.pendingSVCall = true;
|
|
this.interruptsUpdated = true;
|
|
}
|
|
// SXTB
|
|
else if (opcode >> 6 === 0b1011001001) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = signExtend8(this.registers[Rm]);
|
|
}
|
|
// SXTH
|
|
else if (opcode >> 6 === 0b1011001000) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = signExtend16(this.registers[Rm]);
|
|
}
|
|
// TST
|
|
else if (opcode >> 6 == 0b0100001000) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rn = opcode & 0x7;
|
|
const result = this.registers[Rn] & this.registers[Rm];
|
|
this.N = !!(result & 0x80000000);
|
|
this.Z = result === 0;
|
|
}
|
|
// UDF
|
|
else if (opcode >> 8 == 0b11011110) {
|
|
const imm8 = opcode & 0xff;
|
|
this.breakRewind = 2;
|
|
this.rp2040.onBreak(imm8);
|
|
}
|
|
// UDF (Encoding T2)
|
|
else if (opcode >> 4 === 0b111101111111 && opcode2 >> 12 === 0b1010) {
|
|
const imm4 = opcode & 0xf;
|
|
const imm12 = opcode2 & 0xfff;
|
|
this.breakRewind = 4;
|
|
this.rp2040.onBreak((imm4 << 12) | imm12);
|
|
this.PC += 2;
|
|
}
|
|
// UXTB
|
|
else if (opcode >> 6 == 0b1011001011) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.registers[Rm] & 0xff;
|
|
}
|
|
// UXTH
|
|
else if (opcode >> 6 == 0b1011001010) {
|
|
const Rm = (opcode >> 3) & 0x7;
|
|
const Rd = opcode & 0x7;
|
|
this.registers[Rd] = this.registers[Rm] & 0xffff;
|
|
}
|
|
// WFE
|
|
else if (opcode === 0b1011111100100000) {
|
|
deltaCycles++;
|
|
if (this.eventRegistered) {
|
|
this.eventRegistered = false;
|
|
}
|
|
else {
|
|
this.waiting = true;
|
|
}
|
|
}
|
|
// WFI
|
|
else if (opcode === 0b1011111100110000) {
|
|
deltaCycles++;
|
|
this.waiting = true;
|
|
}
|
|
// YIELD
|
|
else if (opcode === 0b1011111100010000) {
|
|
// do nothing for now. Wait for event!
|
|
this.logger.info(LOG_NAME, 'Yield');
|
|
}
|
|
else {
|
|
this.logger.warn(LOG_NAME, `Warning: Instruction at ${opcodePC.toString(16)} is not implemented yet!`);
|
|
this.logger.warn(LOG_NAME, `Opcode: 0x${opcode.toString(16)} (0x${opcode2.toString(16)})`);
|
|
}
|
|
this.cycles += deltaCycles;
|
|
return deltaCycles;
|
|
}
|
|
}
|